Semiconductor chips, such as processor chips, can be housed in chip packages, which are subsequently attached to circuit boards in the manufacture of a number of electronic devices. One common configuration of input/output connections between chips, substrates, packages, and adjacent circuit boards, etc. includes solder connection arrays.
There are a number of design concerns that can be taken into account when forming solder arrays. High mechanical strength and reliability of the solder connections can be desirable. In solder connection arrays, chips, substrates, chip packages, and circuit boards can expand and contract at different rates due to differences in the coefficient of thermal expansion (CTE) in each component. The differences in CTE can cause unwanted stresses and strains in resulting products. Powering up and down and use of the device can result in thermal stress on the components of the device.
One method that has been used to counter thermal stresses due to differences in CTE has been to use underfill compositions, for example between chips and circuit boards or other substrates, that can mitigate differences in CTE and reduce thermal stresses due to operation of the device. Due to miniaturization efforts, circuits are being crowded into smaller geometries. In addition, multiple chips can be crowded into smaller packages. Flip-chip configurations are affected by the miniaturization because mounting space is also shrinking. Consequently, underfill compositions must fill smaller spaces.